To follow yesterdays posting on Resistor Networks, a new page(s) was added to cover SIP Resistor Networks. Same schematics as before but now the pin outs match either a;
6-pin SIP Resistor Network,
8-pin SIP Resistor Network,
10-pin SIP Resistor Network.
This time the components are divided by schematic and not package. So, for example, the bused resistor network is shown on one page, with pinouts for each of the SIP layouts;
SIP Bused Resistor Network. [Common Tie point]
SIP Isolated Resistor Network. [Individual Components]
SIP Dual Termination Resistor Network. [Thevenin]
Looks like there are two general styles of packaging. A molded package and a conformal coated version. The page on SIP Packages shows both package styles.
I also just added a few other pages; one for Non-standard resistors in a 6-pin SIP, and one for a 14-pin DIP Resistor Network. They were all uploaded about an hour ago, but I have to many 'in-work' pages so I'll go ahead and stop for now. I may go ahead and update them again, but will not add any other related pages today. Five new pages works......
Graphic; 8 pin through-hole Single In-line Package [SIP] used with Resistor Networks.
Sunday, November 29, 2009
Saturday, November 28, 2009
What are the different types of Resistor Networks
Had a page out on interfacebus showing a few different schematic diagrams of both Resistor Array and Resistor Networks in a 16 pin Dual In-line Package [DIP]. The page also linked to RC Networks in a 16-pin DIP, and a page which showed the Passive DIP components. Also have a page covering Derating Resistor Networks.
Anyway I added a new page to cover Resistor Networks in a 20-pin Leadless Chip Carrier [LLCC], or 20-pin LLCC Resistor Networks. I then added one to cover 16-pin LLCC Resistor Networks. I think most of the text is all the same on each of the pages. All the schematics are the same, except for the pin out and the packages so why wouldn't the text be the same.
I just noticed that the dual-resistor termination package in a 16-pin LLCC case only has seven termination resistors, what bus uses just 7 bits of data? Same thing with the common-pin package which only has 15 resistors.
So now there's a page for 16-pin DIPs, a 16-pin LCC and a 20-pin LCC package each with three different styles of resistor interconnections.
Design hint. Resistor Networks are great because they save a lot of board space, but there are problems with these components.
First noise is easily passed from one resistor to the next because they are all in the same package.
Secondly, one resistor [in the package] my be located in the correct spot on the PWB, but in many cases all other traces need to be routed out of their way to reach the resistor package. Individual resistor packages can be placed in the exact location required, resistor networks can not. This may not matter in low speed systems but in high speed networks trace distance does matter.
Graphic; Resistor Array, 16-pin Lead-Less Chip Carrier, 8-resistors, no common connection.
Anyway I added a new page to cover Resistor Networks in a 20-pin Leadless Chip Carrier [LLCC], or 20-pin LLCC Resistor Networks. I then added one to cover 16-pin LLCC Resistor Networks. I think most of the text is all the same on each of the pages. All the schematics are the same, except for the pin out and the packages so why wouldn't the text be the same.
I just noticed that the dual-resistor termination package in a 16-pin LLCC case only has seven termination resistors, what bus uses just 7 bits of data? Same thing with the common-pin package which only has 15 resistors.
So now there's a page for 16-pin DIPs, a 16-pin LCC and a 20-pin LCC package each with three different styles of resistor interconnections.
Design hint. Resistor Networks are great because they save a lot of board space, but there are problems with these components.
First noise is easily passed from one resistor to the next because they are all in the same package.
Secondly, one resistor [in the package] my be located in the correct spot on the PWB, but in many cases all other traces need to be routed out of their way to reach the resistor package. Individual resistor packages can be placed in the exact location required, resistor networks can not. This may not matter in low speed systems but in high speed networks trace distance does matter.
Posted by
Leroy
at
8:23 PM
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Labels: Resistor
Friday, November 27, 2009
Component Derating Guidelines
In support of the section on Transistor Derarting, a page was added to explain how to Interpret the derating Curves. Many of the pages already had some text regarding reading the graph, but why keep adding more text to each page if it's the same over and over. The 'How-to' page uses a derating graph from a 2N2904 Transistor, in a TO-39 metal Can.
It was just random chance that I added a picture of a 2N3637 SOA in this posting. I already had a page covering that topic out on Google Sites; Maximum Safe Operating Area.
Normally I don't post new pages added to Google Sites, but I did add two pages today [no text yet]. The internal Construction of a Capacitor, and the internal Construction of a Resistor.
Any other page changes [to either site] today were just small updates.
Graph; Safe Operating Area [SOA] Power Curve, 2N3637 Transistor.
It was just random chance that I added a picture of a 2N3637 SOA in this posting. I already had a page covering that topic out on Google Sites; Maximum Safe Operating Area.
Normally I don't post new pages added to Google Sites, but I did add two pages today [no text yet]. The internal Construction of a Capacitor, and the internal Construction of a Resistor.
Any other page changes [to either site] today were just small updates.
Graph; Safe Operating Area [SOA] Power Curve, 2N3637 Transistor.
Posted by
Leroy
at
8:32 PM
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Labels: Derate, Derating, Transistor
Functional IC Schematics
Yet more Functional schematics for different Integrated Circuits [IC] were added last night.
A page was added to include a Shift Register circuit, with component part numbers. Also one to include a Parity Checker or Parity generator circuit, with just a few part numbers. Another page includes Flip Flop gates. This one does not include gates with Output Enable lines, so I may add another page later to include those types of flip flops.
To support the page on Decoder chips, a page was adder for Encoder Chips. But neither page provides IC part numbers, at least for now.
I think I also added a page on Binary Adders. I may have also added a listing of Analog Switch ICs. Might be about it. As normal, I'll add some more data in a few days. Semiconductor manufacturers, and Standard Logic manufacturers.
Graphic: Dual Analog Switch in a Dual In-Line package, with pinout.
A page was added to include a Shift Register circuit, with component part numbers. Also one to include a Parity Checker or Parity generator circuit, with just a few part numbers. Another page includes Flip Flop gates. This one does not include gates with Output Enable lines, so I may add another page later to include those types of flip flops.
To support the page on Decoder chips, a page was adder for Encoder Chips. But neither page provides IC part numbers, at least for now.
I think I also added a page on Binary Adders. I may have also added a listing of Analog Switch ICs. Might be about it. As normal, I'll add some more data in a few days. Semiconductor manufacturers, and Standard Logic manufacturers.
Graphic: Dual Analog Switch in a Dual In-Line package, with pinout.
Posted by
Leroy
at
11:53 AM
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Labels: IC
Thursday, November 26, 2009
IC Schematics
Even more internal IC schematics were added last night. So far they were all linked off the Multiplexer IC page, but by the end of this posting I'll have added a top level page.
Although I didn't have a circuit diagram for an Analog Switch, I did add one for an Analog Multiplexer IC. One circuit for now, but I my add a few more different configurations of Mux schematics and more data too.
Also added a page for a Clock Buffer. That page only shows one 10-line clock buffer schematic and no information, but I hope to add some part numbers some time today. Some what related to clock buffers, a Data Buffer circuit was added. Just a 16-bit buffer circuit, again with no supporting data.
I new page showing a 4-bit Up/Down Counter was also added. Now the counter page actually has some information attached to it. However that page is still waiting on some part number, but like all these pages I hope to get much of the data input today.
The last page addition was a simple Decode IC circuit.
Ok, well I went ahead and added a top level page to the Logic Design section; IC Functional Circuits.
So in the last few days 10 new pages were added, getting any page views from them is a different matter. These pages will turn into a lot of work while producing no incoming visits like the 2N3418 derating curves. While up-dating that page I noticed that the TO-23 Case page was still sitting at a rank of zero, so I updated it a bit. Same deal with the TO-46 Metal Case.
Graphic; Schmitt Trigger IC, Inverter/Buffer.
Although I didn't have a circuit diagram for an Analog Switch, I did add one for an Analog Multiplexer IC. One circuit for now, but I my add a few more different configurations of Mux schematics and more data too.
Also added a page for a Clock Buffer. That page only shows one 10-line clock buffer schematic and no information, but I hope to add some part numbers some time today. Some what related to clock buffers, a Data Buffer circuit was added. Just a 16-bit buffer circuit, again with no supporting data.
I new page showing a 4-bit Up/Down Counter was also added. Now the counter page actually has some information attached to it. However that page is still waiting on some part number, but like all these pages I hope to get much of the data input today.
The last page addition was a simple Decode IC circuit.
Ok, well I went ahead and added a top level page to the Logic Design section; IC Functional Circuits.
So in the last few days 10 new pages were added, getting any page views from them is a different matter. These pages will turn into a lot of work while producing no incoming visits like the 2N3418 derating curves. While up-dating that page I noticed that the TO-23 Case page was still sitting at a rank of zero, so I updated it a bit. Same deal with the TO-46 Metal Case.
Graphic; Schmitt Trigger IC, Inverter/Buffer.
Posted by
Leroy
at
11:51 AM
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Labels: IC
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