Issues Realting to How to Derate Transistors and Resulting Failures

There are two main pages in this section of the web site; How to derate Transistors by Temperature [Power x Temperature], and Diode Derating [Current x Temperature]. An interrelated page details how to read and Interpret Temperature Derating Curves, which works for diodes or transistors.

 One of the new pages covers component mounting consideration, as Lead Length vs Thermal Resistance [power dissipation for leaded parts]. This particular topic shows why lead length is an important consideration in component power dissipation [in addition to increased circuit inductance]. A companion page covers Copper Pad Area vs Thermal Resistance, to address surface mount components.

The second new page covers Junction Temperature and Wirebond Life, the bond holding the wire between the semiconductor chip and package lead frame. Wire-Bond failure rate vs junction temperature is another way to cover the same topic as the derating charts already do; However, some derating curves do cover ambient temperature, heat-sink temperature and case temperature, in addition to junction temperature.

Related links include Maximum Safe Operating Area,
Over the last 30 days I have added almost 30 new pages, but they were so inter-related that I didn't think blogging about them would really help. Either each blog posting would read almost the same or they would have had almost no text. So I'll generated a new xml site-map for Google in a few weeks to catch the new pages, or wait until Google reads the pages their linked from. In the mean time I have been adding links to the new pages to the human readable [html] sitemap that covers the site [Engineering Site-Map].

So these are two of the nearly 30 new pages added over the last month. I may add them in a larger posting rather than one posting per new page.

TO-276 Three-Terminal Surface Mount Package

What is a TO-276 device?
A 3-Terminal Surface Mount Component, shown on; TO-276 Transistor Package.
As discussed on that page the package may be used for any number of different semiconductors, but the term transistor is used in general. As with all the other related packages the TO-276 page is linked off the Transistor Packages page.

There's not much left to say, as this posts relates to the last two previous posts, which have already covered every thing.

This is the first surface mount package added to that section of the web site, all the other pages cover some type of through hole package. However I have had pending data on several other surface mount styles but the data has not been added yet because I been working other site issues ~ I'm not sure if I can add yet another package type in the next few days or not. Of course the Site-Map was also up-dated.

Transistor Die Bonding

Derate a BJT by Temperature

I've posted about adding some pages covering transistor derating, but I never really linked any of the new pages here. I don't have any new pages to blog about, so I'll list a few of the pages covering transistor derating.

These are just a random sampling of a few pages;
2N2484 PNP Transistor.
2N2906 NPN Transistor.
2N3743 PNP Transistor.
2N4029 PNP Transistor.
2N6676 NPN Transistor.

There's nothing special about these pages, in fact a few seemed to be some of the smaller pages in the group. But they each point to other pages with the same or similar device in a different package style. So I'm really pointing to a dozen pages while only listing 5 here.

These pages were added around the first of December, and up-dated once to add more data. Looks like a few could still use some more data, but I'll be up-dating the pages that haven't changed yet.

FET Derating Guidelines

Derating guidelines for a 2N7000 Field Effect Transistor [FET] was added; 2N2700 Derating.
Unlike the other pages within the FET Derating section, this page only offers recommendations.
All the other pages, or many of them, provide derating curves that should be considered as absolute rules rather than recommendations.
Of course a FET is a style of Transistor, which are covered on the Transistor Derating Guidelines.

The over-all section is Component Derating, if you see a table than it's a guideline, while a curve will imply a rule. The goal is to not exceed the devices junction temperature.

The 2N27002 FET is also covered on the page link.
The 2N7000 device is a plastic TO-92 package, while the 2N7002 is a SOT23 plastic package.

Of course Connector derating guidelines and Cable derating guidelines are also provided within this section, neither of which have a semiconductor junction. Their package or molding is being derated. A Thermal Couple is used to monitor the body of the package for temperature increases. There's a limit to the number of wires in a cable or pins on a connector that can carry some amount of current. Sure one pin may handle an amp of current, but if the connector or cable has 50 leads, does it imply that the component can deal with 50 amps of heat dissipation [no].

For reference;
2N6770 Maximum Case Temperature.
2N6768 Maximum Case Temperature.
2N6766 Maximum Case Temperature.
2N6764 Maximum Case Temperature.